Intel’s 14nm Broadwell chip reverse engineered, reveals impressive FinFETs, 13-layer design

Intel’s 14nm Broadwell chip reverse engineered, reveals impressive FinFETs, 13-layer design
When Intel announced the details on its 14nm process last year, it raised eyebrows in some circles by claiming some extremely aggressive scaling figures. Put simply, Intel stated that it would deliver a better 14nm process with superior characteristics, die size, and overall efficiency than any competitive product TSMC, its largest foundry competitor, would release on 20nm. This predictably kicked off a PR blizzard between the two companies.

Intel stated that it would bring 14nm in with substantial scaling in transistor fin pitch, transistor gate pitch, and interconnect pitch, with a further significant reduction in SRAM scaling. Now, independent analysis and reverse engineering from Chipworks has confirmed that Intel did indeed deliver on its technological promises. Gate pitch has been measured at ~70nm, fin pitch at ~42nm, and a more complex 13-layer metal design. Intel had previously stuck with nine-layer designs before stepping up to 11 for its Bay Trail SoC.

The FinFET transistors of a 14nm Broadwell chip, as seen from above in plan view. [Image credit: Chipworks]

Image courtesy of RealWorldTech. As chip designs shrink, metal layers have become more complicated

Metal layers inside a chip are used to connect various features and areas of the chip. As chips have gotten smaller it’s become increasingly difficult to route wires in ways that don’t obviate the increased performance of the transistors themselves. Intel’s decision to step up to a 13-layer design may be partly responsible for Broadwell’s difficulties; the more metal layers you have to connect the more difficult it is to design the chip efficiently.
The one potential slip that Chipworks notes is that while Intel claimed a 52nm interconnect pitch, they measured 54nm — but they also say that this is within the margin of measurement error, and that Intel may have simply measured from a different point of the die. They also confirm that Intel hit its SRAM cell target size of 0.058 µm².

A 14nm Broadwell chip, side-on, showing all 13 layers

Another shot of the fins of the 14nm Broadwell FinFET transistors

What does this mean for Broadwell?

So, what’s the big picture mean for Intel’s hardware? It means that I’m more inclined to think that the problems of the Lenovo Yoga 3 Pro are either caused by Lenovo’s design decisions or by power management software. OS level drivers could also be an issue. Accurately hitting its process node targets doesn’t necessarily say anything about the underlying chip — Broadwell might still use more power than Intel projected, for example, or it might not reach target frequencies. It might hit all these metrics but have trouble with yields.
At the very least, this data suggests that Intel was playing it straight when it declared its 14nm technology would be a huge step forward and match historic scaling goals. Whether or not Intel can parley those advantages into improving its cost structure and wafer costs is still a very open question. With 450mm wafers on hold and EUV still uncertain, the higher cost at each additional node could still poison any semiconductor manufacturers’ attempts to push to lower process technologies — it’s just not clear when that will happen.
Here’s what I suspect it means, strictly speaking for myself: Broadwell may well push down into power envelopes that compete with “little core” products, but the user experience people get will be very dependent on what kind of design choices the OEM makes. An improperly-cooled Broadwell may indeed feel like an Atom. A well-cooled design should be quite a bit stronger. Ultimately, however, Broadwell doesn’t break the laws of physics — and the laws of physics dictate rather strongly that there’s a heat cost for every degree of computation you perform. At a certain point, Broadwell’s “big core” scale-down and Atom’s “little-core” scale up are going to meet and match each other.